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1998 data sheet 1998 mips technologies inc. mos integrated circuit v r 10000 tm , v r 12000 tm 64-bit microprocessors m pd30700,30700l,30710 description the m pd30700 and 30700l (v r 10000) and m pd30710 (v r 12000) are new members of necs v r series tm risc (reduced instruction set computer) microprocessors. these new high-performance 64-bit microprocessors employ a new risc architecture developed by mips tm , andes tm architecture. the v r 10000 and v r 12000 are designed to be used in high-performance computers and achieve considerably higher processing speed through the employment of a super scalar pipeline. remark andes: architecture with non-sequential dynamic execution scheduling the functions of these microprocessors are described in detail in the following manuals. be sure to read these manuals when designing systems. v r 10000, v r 12000 users manual : u10278e v r 5000 tm , v r 10000 users manual - instruction : u12754e features ? mips 64-bit risc architecture ? high-speed operation processing super scalar pipeline executing five instructions in parallel ? 14specint95, 23specfp95 ? 17specint95, 27specfp95 ? instruction set upward-compatible with v r 4000 tm , v r 4200 tm , and v r 4400 tm (conforms to mips-i/ii/iii/iv) ? high-speed translation lookaside buffer (tlb) (64 double entries) ? address space physical: 40 bits virtual: 44 bits ? floating-point unit (fpu) ? primary cache memory (32k bytes for each of instruction and data, 2-way set associative) ? secondary cache memory interface ? 128-bit secondary cache interface ? ssram interface (v r 10000: 250 mhz max., v r 12000: 200 mhz max.) ? supports up to 16m bytes ? operating frequency ? internal: 250 mhz max. ? external: 250 mhz max. ? external/internal multiplication factor selectable from 1 to 4 ? internal: 300 mhz max. ? external: 150 mhz max. ? external/internal multiplication factor selectable from 2 to 10 ? multi-processor function ? up to four buses of cluster connection can be connected. ? supply voltage v dd = 3.3 v 0.165 v ( m pd30700) v dd = 2.6 v 0.1 v ( m pd30700l) v dd = 2.6 v 0.1 v ( m pd30710) unless otherwise specified, the v r 10000 is treated as the representative model throughout this document. the information in this document is subject to change without notice. date no. u12703ej1v0ds00 (1st edition) date published june 1998 n cp(k) printed in japan
2 m pd30700,30700l,30710 applications ? unix tm servers ? windows nt tm servers ? desktop workstations, etc. ordering information part number package maximum internal operating frequency m pd30700rs-180 599-pin ceramic lga 180 m pd30700rs-200 599-pin ceramic lga 200 m pd30700lrs-225 note 599-pin ceramic lga 225 m pd30700lrs-250 note 599-pin ceramic lga 250 m pd30710rs-300 note 599-pin ceramic lga 300 note under development remark lga: land grid array
3 m pd30700,30700l,30710 pin configuration 599-pin ceramic lga m pd30700rs-180 m pd30700rs-200 m pd30700lrs-225 m pd30700lrs-250 m pd30710rs-300 1 ar an al aj ag ae ac aa w u r n l j g e c a ap am ak ah af ad ab y v t p m k h f d b index 2468 10 12 14 16 18 20 22 24 26 28 30 32 34 3579 11 13 15 17 19 21 23 25 27 29 31 33 35 35 33 31 29 27 25 23 21 19 17 15 13 11 97531 34 32 30 28 26 24 22 20 18 16 14 12 10 8642 top view bottom view
4 m pd30700,30700l,30710 (1/4) no. name no. name no. name no. name a1 C b9 scadcs c17 sysad41 d25 v ss a2 v dd b10 scaaddr5 c18 v dd d26 v dd a3 v ss b11 v ss c19 sysad36 d27 scdata68 a4 v dd qsc b12 scdata78 c20 sysad32 d28 scdata64 a5 scdata89 b13 scclk0 c21 v ss d29 v ss a6 scdata85 b14 v dd c22 v ss d30 scaaddr12 a7 v ss b15 scdata72 c23 sysclkret d31 scaaddr16 a8 scadwr b16 sysad44 c24 v ss d32 v ss a9 scaaddr8 b17 v ss c25 v dd pa d33 scdatachk0 a10 v dd qsc b18 sysad40 c26 scdata71 d34 scdata29 a11 scaaddr1 b19 v ss c27 v ss d35 v dd qsc a12 scdata76 b20 sysad33 c28 scdata67 e1 scclk5 a13 v ss b21 v ss c29 scdatachk2 e2 v ss a14 scdata74 b22 dcok c30 v dd qsc e3 v dd a15 sysad46 b23 sysclkret c31 scaaddr13 e4 scdatachk6 a16 v dd qsys b24 v ss pa c32 scaaddr18 e5 v dd a17 sysad42 b25 v ss pa c33 v dd qsc e6 scdata90 a18 sysad37 b26 scclk1 c34 v dd e7 scdata86 a19 sysad35 b27 scdatachk9 c35 v ss e8 v dd qsc a20 v dd qsys b28 v dd d1 v dd qsc e9 scdata80 a21 v ss b29 scdata65 d2 sctcs e10 scadway a22 sysclk b30 scaaddr9 d3 scdatachk8 e11 v ss a23 sysclk b31 v ss d4 v ss e12 scaaddr4 a24 v ss pa b32 scaaddr15 d5 scdata92 e13 scaaddr0 a25 nc b33 scaaddr17 d6 scdata88 e14 v dd qsc a26 scclk1 b34 v ss d7 v ss e15 scclk0 a27 v ss b35 v dd d8 scdata82 e16 sysad47 a28 scdata70 c1 v ss d9 scadoe e17 v ss a29 v ss c2 v dd d10 v dd e18 sysad39 a30 scdatachk4 c3 v dd qsc d11 scaaddr6 e19 v ss a31 scaaddr11 c4 scdata94 d12 scaaddr2 e20 syscyc a32 v dd qsc c5 scdata91 d13 v ss e21 v ss a33 v ss c6 v dd qsc d14 scdata77 e22 v dd pd a34 v dd c7 scdata84 d15 scdata73 e23 v ss a35 v ss c8 scdata81 d16 v dd e24 v ss b1 v dd c9 v ss d17 sysad43 e25 v ss b2 v ss c10 scaaddr7 d18 sysad38 e26 scdata69 b3 scdata95 c11 scaaddr3 d19 sysad34 e27 scdata66 b4 scdata93 c12 v dd qsc d20 v dd e28 v dd qsc b5 v ss c13 scdata79 d21 v ss e29 scaaddr10 b6 scdata87 c14 scdata75 d22 v ss pd e30 scaaddr14 b7 scdata83 c15 v ss d23 v ss e31 v dd b8 v dd c16 sysad45 d24 v ss e32 scdata31 note connect this pin via a100- w resistor.
5 m pd30700,30700l,30710 (2/4) no. name no. name no. name no. name e33 v dd k1 v dd qsc p4 sctag6 v32 sysad6 e34 v ss k2 sctag14 p5 v dd qsc v33 v dd e35 scdata27 k3 sctag17 p31 v dd qsc v34 sysad4 f1 v dd k4 v dd p32 scdata4 v35 sysad2 f2 sctwr k5 sctag19 p33 scdata2 w1 scclk4 f3 v dd qsc k31 scdata18 p34 v dd w2 v ss f4 scclk5 k32 v dd p35 sysad15 w3 sctagchk1 f5 v ss note k33 scdata16 r1 sctag0 w4 scclk4 f31 scdata30 k34 scdata11 r2 v dd qsc w5 v ss f32 scdata28 k35 v dd qsc r3 v ss w31 v ss f33 v dd qsc l1 sctag12 r4 sctag1 w32 sysad1 f34 scdata25 l2 v ss r5 sctag3 w33 jtck f35 scdata23 l3 v dd r31 scdata0 w34 v ss g1 v ss l4 sctag15 r32 sysad13 w35 jtdi g2 sctag22 l5 v ss r33 v ss y1 v cc qsys g3 sctag24 l31 v ss r34 sysad14 y2 syscmd0 g4 v ss l32 scdata14 r35 sysad12 y3 syscmd1 g5 sctoe l33 scdata9 t1 v dd qsc y4 v dd g31 scdata26 l34 v ss t2 nc y5 syscmd3 g32 v ss l35 scdata7 t3 sctway y31 jtdo g33 scdata21 m1 sctag7 t4 v dd y32 v dd g34 scdata19 m2 sctag9 t5 sctaglsbaddr y33 vrefsys g35 v ss m3 v dd qsc t31 sysad11 y34 sysad0 h1 sctag20 m4 sctag11 t32 v dd y35 v dd qsys h2 v dd m5 sctag13 t33 sysad9 aa1 syscmd2 h3 v dd qsc m31 scdata12 t34 sysad10 aa2 syscmd4 h4 sctag25 m32 scdata10 t35 v dd qsys aa3 v ss h5 v dd qsc m33 v dd qsc u1 sctagchk6 aa4 syscmd5 h31 v dd qsc m34 scdata5 u2 v ss aa5 syscmd7 h32 scdata24 m35 scdata3 u3 sctagchk5 aa31 scclk2 h33 v dd qsc n1 v ss u4 v ss note aa32 scdata32 h34 v dd n2 sctag5 u5 v ss aa33 v ss h35 scdata17 n3 sctag8 u31 v ss aa34 jtms j1 sctag16 n4 v ss u32 sysad7 aa35 vrefsc j2 sctag18 n5 sctag10 u33 sysad5 ab1 syscmd6 j3 v ss n31 scdata8 u34 v ss ab2 v dd j4 sctag21 n32 v ss u35 sysad8 ab3 syscmd8 j5 sctag23 n33 scdata6 v1 sctagchk4 ab4 syscmd10 j31 scdata22 n34 scdata1 v2 sctagchk2 ab5 v dd qsys j32 scdata20 n35 v ss v3 v dd ab31 v dd qsc j33 v ss p1 sctag2 v4 sctagchk0 ab32 scdata35 j34 scdata15 p2 v dd v5 sctagchk3 ab33 scclk2 j35 scdata13 p3 sctag4 v31 sysad3 ab34 v dd note connect this pin via a100- w resistor.
6 m pd30700,30700l,30710 (3/4) no. name no. name no. name no. name ab35 scdata33 ag3 v ss al6 scdata124 am14 scdata110 ac1 v ss ag4 sysgblperf al7 scdata120 am15 scclk3 ac2 syscmd9 ag5 syswrrdy al8 v dd qsc am16 v dd ac3 syscmdpar ag31 scdata53 al9 scdata114 am17 sysad58 ac4 v ss ag32 scdata51 al10 scbdoe am18 sysad54 ac5 sysreq ag33 v ss al11 scbaddr8 am19 sysad52 ac31 scdata39 ag34 scdata48 al12 scbaddr4 am20 v dd ac32 v ss ag35 scdata46 al13 scbaddr0 am21 sysadchk4 ac33 scdata37 ah1 sysresp2 al14 v dd qsc am22 sysad30 ac34 scdata34 ah2 v dd al15 scdata106 am23 v ss ac35 v ss ah3 v dd qsys al16 scdata104 am24 sysad26 ad1 syscmd11 ah4 sysstatepar al17 sysad60 am25 sysad22 ad2 sysval ah5 v dd qsys al18 sysad56 am26 v dd ad3 v dd qsys ah31 v dd qsc al19 sysad50 am27 scdata102 ad4 sysgnt ah32 scdata55 al20 sysadchk6 am28 scdata98 ad5 sysreset ah33 v dd qsc al21 sysadchk2 am29 v ss ad31 scdata43 ah34 v dd al22 v dd qsys am30 scbaddr11 ad32 scdata41 ah35 scdata50 al23 sysad28 am31 scbaddr15 ad33 v dd qsc aj1 v ss al24 sysad24 am32 v ss ad34 scdata38 aj2 sysresp0 al25 sysad20 am33 scdata63 ad35 scdata36 aj3 sysrdrdy al26 sysad16 am34 scdata62 ae1 sysrel aj4 v ss al27 scdata100 am35 v dd qsc ae2 v ss aj5 sysstate1 al28 v dd qsc an1 v ss ae3 v dd aj31 scdata57 al29 scbaddr9 an2 v dd ae4 sysresppar aj32 v ss al30 scbaddr13 an3 v dd qsc ae5 v ss aj33 scdata54 al31 v dd an4 scdatachk7 ae31 v ss aj34 scdata52 al32 scdatachk1 an5 scdata125 ae32 scdata45 aj35 v ss al33 v dd an6 v dd qsc ae33 scdata42 ak1 sysstateval al34 v ss an7 scdata118 ae34 v ss ak2 sysstate2 al35 scdata60 an8 scdata115 ae35 scdata40 ak3 v dd qsys am1 v dd qsys an9 v ss af1 v dd qsys ak4 syscorerr am2 sysuncerr an10 scbdcs af2 dcok ak5 sysnmi am3 v ss note an11 scbaddr5 af3 sysresp3 ak31 scdata61 am4 v ss an12 v dd qsc af4 v dd ak32 scdata59 am5 scdata126 an13 scdata109 af5 sysresp1 ak33 v dd qsc am6 scdata122 an14 scdata108 af31 scdata49 ak34 scdata58 am7 v ss an15 v ss af32 v dd ak35 scdata56 am8 scdata116 an16 sysad62 af33 scdata47 al1 sysstate0 am9 scdata112 an17 sysad59 af34 scdata44 al2 v ss am10 v dd an18 v dd af35 v dd qsc al3 v dd am11 scbaddr6 an19 sysad51 ag1 sysrespval al4 v ss note am12 scbaddr2 an20 sysad48 ag2 sysresp4 al5 v dd am13 v ss an21 v ss note connect this pin via a100- w resistor.
7 m pd30700,30700l,30710 (4/4) no. name no. name no. name no. name an22 sysadchk0 ap8 v dd ap29 scdata97 ar15 sysad63 an23 sysad29 ap9 scbdwr ap30 scbaddr10 ar16 v dd qsys an24 v dd qsys ap10 scbaddr7 ap31 v ss ar17 sysad57 an25 sysad21 ap11 v ss ap32 scbaddr16 ar18 sysad55 an26 sysad18 ap12 scbaddr1 ap33 scbaddr17 ar19 sysad49 an27 v ss ap13 scdata107 ap34 v ss ar20 v dd qsys an28 scdata99 ap14 v dd ap35 v dd ar21 sysadchk5 an29 scdata96 ap15 scdata105 ar1 v ss ar22 sysadchk1 an30 v dd qsc ap16 sysad61 ar2 v dd ar23 v ss an31 scbaddr14 ap17 v ss ar3 v ss ar24 sysad27 an32 scbaddr18 ap18 sysad53 ar4 v ss qsc ar25 sysad23 an33 v dd qsc ap19 v ss ar5 scdata123 ar26 v dd qsys an34 v dd ap20 sysadchk7 ar6 scdata119 ar27 sysad17 an35 v ss ap21 sysadchk3 ar7 v ss ar28 scdata101 ap1 v dd ap22 v dd ar8 scdata113 ar29 v ss ap2 v ss ap23 sysad31 ar9 scbdway ar30 scdatachk3 ap3 scdatachk5 ap24 sysad25 ar10 v dd qsc ar31 scbaddr12 ap4 scdata127 ap25 v ss ar11 scbaddr3 ar32 v dd qsc ap5 v ss ap26 sysad19 ar12 scdata111 ar33 v ss ap6 scdata121 ap27 scdata103 ar13 v ss ar34 v dd ap7 scdata117 ap28 v dd ar14 scclk3 ar35 v ss
8 m pd30700,30700l,30710 pin names dcok : dc voltage ok jtck : jtag clock jtdi : jtag serial data input jtdo : jtag serial data output jtms : jtag mode select scaaddr (18 : 0), scbaddr (18 : 0) : secondary cache address bus scadcs, scbdcs : secondary cache data chip select scadoe, scbdoe : secondary cache data output enable scadway, scbdway : secondary cache data way scadwr, scbdwr : secondary cache data write enable scclk (5 : 0), scclk (5 : 0) : secondary cache clock scdata (127 : 0) : secondary cache data bus scdatachk (9 : 0) : secondary cache data check bus sctag (25 : 0) : secondary cache tag bus sctagchk (6 : 0) : secondary cache tag check bus sctaglsbaddr : secondary cache tag lsb address sctcs : secondary cache chip select sctoe : secondary cache tag output enable sctway : secondary cache tag way sctwr : secondary cache tag write enable sysad (63 : 0) : system address/data bus sysadchk (7 : 0) : system address/data check bus sysclk, sysclk : system clock sysclkret, sysclkret : system clock return syscmd (11 : 0) : system command bus syscmdpar : system command bus parity syscorerr : system correctable error syscyc : system cycle sysgbperf : system globally performed sysgnt : system grant sysnmi : system non-maskable interrupt sysrdrdy : system read ready sysreset : system reset sysresp (4 : 0) : system response bus sysresppar : system response bus parity sysrespval : system response bus valid sysuncerr : system uncorrectable error sysval : system valid syswrrdy : system write ready sysrel : system release sysreq : system request
9 m pd30700,30700l,30710 sysstate (2 : 0) : system state bus sysstatepar : system state bus parity sysstateval : system state bus valid v dd : power supply v dd pa : v dd for the pll analog v dd pd : v dd for the pll digital v dd qsc : v dd for the secondary cache v dd qsys : v dd for the system interface vrefsc : voltage reference for the secondary cache vrefsys : voltage reference for the system interface v ss : ground v ss pa : v ss for the pll analog v ss pd : v ss for the pll digital nc : no connection
10 m pd30700,30700l,30710 block diagram main memory, i/o system bus branch unit clock instruction decode register mapping integer register 64 fp register 64 external agent/ cluster controller switch secondary cache secondary cache (512k bytes to 16m bytes) ssram 19 + way secondary cache address tag 26 + 7 data 128 + 10 tlb address generation alu1 alu2 adder v r 10000 multiplier address queue integer queue instruction cache 32k bytes 2-way set associative system interface up to four v r 10000s can be directly connected. secondary cache memory interface address 32-bit instruction fetch 4 address 64-bit load/store data cache 32k bytes 2-way set associative fp queue
11 m pd30700,30700l,30710 table of contents 1. pin functions ........................................................................................................................... 13 1.1 pin function list ................................................................................................................. 13 1.2 recommended connection of unused pins ................................................................... 16 2. cpu internal architecture .............................................................................................. 17 2.1 pipeline ............................................................................................................................... .. 17 2.1.1 configuration ............................................................................................................................. 17 2.1.2 operation ............................................................................................................................... .... 18 2.2 cpu registers (virtual registers) ...................................................................................... 19 2.3 system control coprocessor (cp0) ................................................................................. 20 2.3.1 cp0 registers ............................................................................................................................. 20 2.4 data format and addressing ............................................................................................ 22 2.5 virtual storage ..................................................................................................................... 24 2.5.1 virtual address space ................................................................................................................ 24 2.5.2 address translation ................................................................................................................... 27 2.6 cache ............................................................................................................................... ..... 29 2.6.1 primary cache ............................................................................................................................ 29 2.6.2 secondary cache ....................................................................................................................... 29 3. fpu internal architecture ............................................................................................... 30 3.1 internal function block ...................................................................................................... 30 3.2 fpu registers ...................................................................................................................... 30 3.3 data format ......................................................................................................................... 31 4. interface ............................................................................................................................... .... 32 4.1 system interface ................................................................................................................. 32 4.1.1 setting operating frequency of system interface ..................................................................... 32 4.2 secondary cache interface ............................................................................................... 33 4.3 clock interface .................................................................................................................... 33 4.3.1 system interface clock and processor clock ............................................................................ 33 4.3.2 secondary cache clock ............................................................................................................. 33 4.4 system configuration example ........................................................................................ 33 4.4.1 uni-processor system ............................................................................................................... 33 4.4.2 multi-processor system ............................................................................................................. 35 4.5 btmc interface .................................................................................................................... 36 4.6 dsd (delay speculative dirty) mode (v r 12000 only) ..................................................... 38 4.6.1 dsd mode delay ....................................................................................................................... 38 4.6.2 secondary cache status in dsd mode .................................................................................... 38 4.6.3 other features ............................................................................................................................ 38 5. internal/external control functions ....................................................................... 39 5.1 reset function .................................................................................................................... 39 5.1.1 power-on reset and cold reset ................................................................................................ 39 5.1.2 software reset ........................................................................................................................... 39 5.2 interrupt functions ............................................................................................................. 39 5.3 jtag function ..................................................................................................................... 40
12 m pd30700,30700l,30710 6. instruction set ...................................................................................................................... 41 6.1 instruction formats ............................................................................................................ 41 6.2 cpu instruction set list .................................................................................................... 41 6.3 fpu instruction set list ..................................................................................................... 46 6.4 delay of instruction ............................................................................................................ 49 7. electrical specifications ................................................................................................. 50 8. push-pull output buffer circuit .................................................................................. 64 9. package drawing ................................................................................................................... 65
13 m pd30700,30700l,30710 1. pin functions 1.1 pin function list (1/3) pin name i/o function scclk (5 : 0) output secondary cache clock signals. scclk (5 : 0) output secondary cache clock signals. inverted scclk (5:0) signals. scaaddr (18 : 0), output secondary cache address bus. scbaddr (18 : 0) 19-bit address bus for secondary cache. sctaglsbaddr output secondary cache tag lsb address. specifies the lsb address of a secondary cache tag. scadway, output secondary cache data way. scbdway specifies a way of secondary cache data. scdata (127 : 0) i/o secondary cache data bus. 128-bit bus to read or write data from or to the secondary cache. scdatachk (9 : 0) i/o secondary cache data check bus. 10-bit bus used to read or write ecc and even parity for secondary cache data. scadoe, output secondary cache data output enable. scbdoe signals enabling output of secondary cache data. scadwr, output secondary cache data write enable. scbdwr signals enabling writing of secondary cache data. scadcs, output secondary cache data chip select. scbdcs signals enabling access of secondary cache data. sctway output secondary cache tag way. specifies the way of a secondary cache tag. sctag (25 : 0) i/o secondary cache tag bus. 26-bit bus to read or write a tag to or from the secondary cache. sctagchk (6 : 0) i/o secondary cache tag check bus. 7-bit bus used to read or write ecc for secondary cache tag. sctoe output secondary cache tag output enable. signal enabling output of a secondary cache tag. sctwr output secondary cache tag write enable. signal enabling writing of a secondary cache tag. sctcs output secondary cache tag chip select. signal enabling access to a secondary cache tag. sysclk input system clock. system clock input. sysclk input system clock. system clock input. inverted sysclk signal. sysclkret output system clock. system clock output used for termination of system clock. sysclkret output system clock. system clock output used for termination of system clock. inverted sysclkreset signal. sysreq output system request. signal requesting enabling issuance of a processor request when the v r 10000 serves as a slave.
14 m pd30700,30700l,30710 (2/3) pin name i/o function sysgnt input system enable. signal used by an external agent to request the v r 10000 for use of the system interface. sysrel i/o system release. the master side of the system interface asserts this signal active for the duration of 1 sysclk cycle when it releases the right to use the system interface in the subsequent sysclk cycle. sysrdrdy input system read ready. indicates that the external agent is ready to accept a processor read request and upgrade request. syswrrdy input system write ready. indicates that the external agent is ready to accept a processor write request and processor eliminate request. sysad (63 : 0) i/o system address/data bus. 64-bit address/data bus for communication between the v r 10000 and external agent. sysadchk (7 : 0) i/o system address/data check bus. 8-bit ecc bus for sysad bus. syscmd (11 : 0) i/o system command bus. 12-bit bus for command communication between the v r 10000 and external agent. syscmdpar i/o system command bus parity. one odd parity bit for the system command bus. sysval i/o system valid. signal indicating that the master side of the system interface drives a valid address/ command/data onto the sysad bus and syscmd bus. sysstate (2 : 0) output system state bus. 3-bit bus indicating issuance or addition of a processor coherent status response. sysstatepar output system state bus parity. one odd parity bit for the system state bus. sysstateval output system state bus valid. the v r 10000 asserts this signal active for the duration of 1 sysclk cycle when it issues a processor coherent response status to the sysstate bus. sysresp (4 : 0) input system response bus. 5-bit bus used by the external agent to issue an external end response. sysresppar input system response bus parity. one odd parity bit for the system response bus. sysrespval input system response bus valid. the external agent asserts this signal active for 1 sysclk cycle when it issues an external end response to the sysresp bus. sysreset input system reset. signal used by the external agent to reset the v r 10000. sysnmi input system non-maskable interrupt. signal used by the external agent to issue nmi. syscorerr output system correctable error. the v r 10000 asserts this signal active for 1 sysclk cycle when it finds and correct a correctable error. sysuncerr output system uncorrectable error. the v r 10000 asserts this signal active for 1 sysclk cycle when it finds an uncorrectable tag error.
15 m pd30700,30700l,30710 (3/3) pin name i/o function sysgblperf input system global perfect. an external agent uses this signal to indicate completion of a processor request to all external agents. syscyc input system cycle. the external agent uses this signal to define a virtual system interface clock in hardware emulation environment. jtdi input jtag data input. inputs jtag serial data. jtdo output jtag data output. outputs jtag serial data. jtck input jtag clock input. inputs jtag serial clock. keep this signal low when the jtag interface is not used. jtms input jtag mode select. selects a mode of jtag. dcok input dc voltage enable. the external agent asserts this signal active when the following signals are stable: v dd , v dd qsc, v dd qsys, v ref sc, v ref sys, v dd pa, v dd pd, sysclk v dd input power supply pin. power supply for the cpu core. v dd qsc input secondary cache v dd . power supply for the output driver of the secondary cache interface. v dd qsys input system interface v dd . power supply for the output driver of the system interface. vrefsc input secondary cache voltage. reference voltage for the input pins of the secondary cache interface. vrefsys input system interface voltage. reference voltage for the input pins of the system interface. v dd pa input pll analog v dd . power supply for the pll analog circuit. v dd pd input pll digital v dd . power supply for the pll digital circuit. v ss input ground potential pin. ground for the cpu core and output driver. v ss pa input pll analog gnd. ground for the pll analog. v ss pd input pll digital gnd. ground for pll digital. nc no connection. leave this pin unconnected.
16 m pd30700,30700l,30710 1.2 recommended connection of unused pins table 1-1 shows the recommended connection of unused pins. table 1-1. recommended connection of unused pins pin name i/o recommended connection jtdi input connect each of these pins to v dd via a resistor. jtck jtms sysnmi connect this pin to v dd qsys via resistor of 100 w or more. sysrdrdy connect each of these pins to v ss via a resistor of 100 w or more. syswrrdy sysgblperf syscyc sysadchk (7 : 0) i/o connect each of these pins to v ss or v dd qsys via a resistor or 100 w or more.
17 m pd30700,30700l,30710 2. cpu internal architecture 2.1 pipeline 2.1.1 configuration the v r 10000 has a 5-way super scalar pipeline as illustrated below. this pipeline can simultaneously fetch and decode four instructions in 1 pcycle. (1) fp addition pipeline (2) fp multiplication pipeline (3) integer alu1 pipeline (4) integer alu2 pipeline (5) load/store pipeline figure 2-1. pipeline 5-instruction parallel execution pipeline fp addition pipeline (fp queue) issue rf fadd-1 fadd-2 issue rf fmpy-1 fmpy-2 fadd-3 fmpy-3 result stage 3 issue stage 2 decode stage 1 fetch stage 4 execute stage 5 execute stage 6 execute stage 7 store result issue rf alu1 result issue rf alu2 result issue rf addr.calc data cache tlb queue branch address instruction fetch, decode (4 instructions/1 cycle) instruction execution primary instruction cache instruction decode integer register operand fp queue, fp register result fp multiplication pipeline (fp queue) integer alu1 pipeline (integer queue) integer alu2 pipeline (integer queue) load/store pipeline (address queue) 7 pipeline stages branch unit
18 m pd30700,30700l,30710 2.1.2 operation the pipeline of the v r 10000 has seven stages. the operation of each stage is described below: (1) stage 1 (fetch) four instructions are fetched in 1 cycle and stored to the instruction register. (2) stage 2 (decode) the four instructions fetched in stage 1 are decoded. (3) stage 3 (issue) the decoded instructions are written to a queue. the v r 10000 has an fp queue, integer queue, and address queue. in addition, an operand is read from the register file. (4) stage 4 through stage 6 (execute) the instructions are executed. the execution pipeline and execution cycle differ depending on the type of instruction. (a) fp addition pipeline executes floating-point addition instructions in 3 pcycle. (b) fp multiplication pipeline executes floating-point multiplication, division, and square root instructions in 3 pcycle. (c) integer alu1 pipeline executes integer addition, subtraction, shift, and logic instructions in 1 pcycle. (d) integer alu2 pipeline executes integer addition, subtraction, and logic instructions in 1 pcycle. (e) load/store pipeline generates a memory address used for integer or floating-point load/store instructions. (5) stage 7 (store) the results of executing the instructions are stored to registers.
19 m pd30700,30700l,30710 2.2 cpu registers (virtual registers) figure 2-2 shows the cpu registers of the v r 10000. physically, sixty-four general-purpose registers are available. of these, however, only thirty-two can be accessed by software or an external agent. mapping of the other registers is automatically controlled by the cpu. the bit width of a register is determined by the operation mode of the v r 10000 (32 bits in 32-bit mode, or 64 bits in 64-bit mode). of the thirty-two general-purpose registers, the following two have special meanings. ? register r0 : the contents of this register are always 0. register r0 can be used as the target register of an instruction when the result of an operation is to be discarded. this register can also be used as a source register when the value of 0 is necessary. ? register r31 : this is a link system for the jal and jalr instructions. therefore, do not use this register with any other instructions. two multiplication/division registers (hi and lo) are used to store the result of integer multiplication, or quotient (lo) and remainder (hi) resulting from integer division. the load link register is used to synchronize two or more v r 10000s in a multi-processor system. figure 2-2. cpu registers there is no program status word (psw). the function of psw is substituted by the status register and cause register incorporated into the system control coprocessor (cp0). 63 0 63 0 63 0 r0 = 0 r1 r2 r29 r30 r31 (link address) hi lo pc 0 load link register llbit 63 0 general-purpose registers multiplication/division register program counter
20 m pd30700,30700l,30710 2.3 system control coprocessor (cp0) the cp0 registers/cp0 instructions access the tlb and cache. manipulating a mode in which the v r 10000 is used, exceptions, and interrupts are also controlled by the cp0. in addition, the cp0 also has a test/debug function. 2.3.1 cp0 registers all the cp0 registers that can be used with the v r 10000 are listed below. writing or reading an unused register (rfu) is undefined. figure 2-3. cpu0 registers and tlb remark * indicates a register number. entry lo0 2* entry hi 10* entry lo1 3* index 0* random 1* page mask 5* wired 6* config 16* watch hi 19* ecc 26* pc 25* frame mask 21* tlb 63 00 127/255 ("safe" entry) context 4* badvaddr 8* count 9* compare 11* cause 13* status 12* epc 14* prld 15* watch lo 18* x context 20* lladdr 17* tag hi 29* cache error 27* diagnosis 22* tag lo 28* error epc 30* registers used by memory management system registers used for exception processing
21 m pd30700,30700l,30710 table 2-1. cp0 register list no. register description 0 index tlb entry programmable pointer 1 random tlb entry random pointer 2 entry lo0 second half of tlb entry for even number vpn 3 entry lo1 second half of tlb entry for odd number vpn 4 context pointer to virtual pte table of kernel in 32-bit mode 5 page mask tlb page mask 6 wired number of wired tlb entries 7 rfu (reserved for future use) 8 badvaddr virtual address at which last error has occurred 9 count timer count 10 entry hi first half of tlb entry (including vpn and asid) 11 compare timer comparison 12 status status register 13 cause cause of last exception 14 epc exception program counter 15 prld processor revision identifier 16 config configuration register 17 lladdr address of ll instruction 18 watch lo low-order bits of memory reference trap address 19 watch hi high-order bits of memory reference trap address 20 x context pointer to virtual pte table of kernel in 64-bit mode 21 frame mask bit mask of entry lo register 22 diagnosis branch diagnosis 23, 24 rfu 25 pc performance counter 26 ecc ecc of secondary cache and parity of primary cache 27 cache error index of cache error and status field 28 tag lo cache tag register, low-order 29 tag hi cache tag register, high-order 30 error epc error exception program counter 31 rfu
22 m pd30700,30700l,30710 2.4 data format and addressing the v r 10000 has the following four types of data formats: double word (64 bits) word (32 bit) half word (16 bits) byte (8 bits) if the data format is double word, word, or half word, the byte order can be set to bit endian or little endian by using the be bit of the config register. figure 2-4. byte address in word: big endian remarks 1. the most significant byte is the least significant address. 2. a word is addressed by the address of the most significant byte. figure 2-5. byte address in word: little endian remarks 1. the least significant byte is the least significant address. 2. a word is addressed by the address of the least significant byte. 31 24 23 16 15 8 7 0 high-order address low-order address 12 13 14 15 8 9 10 11 456 7 012 3 word address 12 8 4 0 31 24 23 16 15 8 7 0 high-order address low-order address 15 14 13 12 11 10 9 8 765 4 321 0 word address 12 8 4 0
23 m pd30700,30700l,30710 figure 2-6. byte address in double word: big endian remarks 1. the most significant byte is the least significant address. 2. a word is addressed by the address of the most significant byte. figure 2-7. byte address in double word: little endian remarks 1. the least significant byte is the least significant address. 2. a word is addressed by the address of the least significant byte. high-order address low-order address double word address 16 8 0 63 32 31 16 15 0 word half word byte 16 17 8 0 9 1 18 10 2 19 11 3 20 12 4 21 13 5 22 14 6 23 15 7 8 7 16 8 0 63 32 31 0 23 22 15 7 14 6 21 13 5 20 12 4 19 11 3 18 10 2 17 9 1 16 8 0 16 15 8 7 high-order address low-order address double word address word half word byte
24 m pd30700,30700l,30710 2.5 virtual storage 2.5.1 virtual address space the v r 10000 has two operation modes, the 32-bit and 64-bit modes. in addition, it has three operating modes: the user mode, supervisor mode, and kernel mode. figures 2-8 through 2-11 show the virtual address spaces in the respective modes. figure 2-8. user mode address space note in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. 0xffff ffff 32 bits note address error 2g bytes w/tlb mapping useg 64 bits address error 16t bytes w/tlb mapping xuseg 0x8000 0000 0x7fff ffff 0x0000 0000 0xffff ffff ffff ffff 0x0000 1000 0000 0000 0x0000 0fff ffff ffff 0x0000 0000 0000 0000
25 m pd30700,30700l,30710 figure 2-9. supervisor mode address space notes 1. in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. 2. if the ux bit of the status register is 0, 0x0000 0000 8000 0000 through 0x0000 0fff ffff ffff cause an address error. 64 bits address error 0.5g bytes w/tlb mapping address error 16t bytes w/tlb mapping address error 16t bytes note 2 w/tlb mapping xsseg csseg xsuseg 0xffff ffff 32 bits note address error address error 2g bytes w/tlb mapping sseg suseg 0.5g bytes w/tlb mapping 0xe000 0000 0xdfff ffff 0xc000 0000 0xbfff ffff 0x8000 0000 0x7fff ffff 0x0000 0000 0xffff ffff ffff ffff 0xffff ffff e000 ffff 0xffff ffff dfff ffff 0xffff ffff c000 0000 0xffff ffff bfff ffff 0x4000 0000 0000 0000 0x3fff ffff ffff ffff 0x0000 0000 0000 0000 0x4000 1000 0000 0000 0x4000 0fff ffff ffff 0x0000 1000 0000 0000 0x0000 0fff ffff ffff
26 m pd30700,30700l,30710 figure 2-10. kernel mode address space notes 1. in the 32-bit mode, the value of bit 31 is sign-extended to bits 32 through 63. 2. if the sx bit of the status register is 0, this area causes an address error. 3. if the ux bit of the status register is 0, 0x0000 0000 8000 0000 through 0x0000 0fff ffff ffff cause an address error. 64 bits 0.5g bytes w/tlb mapping 0.5g bytes w/tlb mapping 0.5g bytes w/o tlb mapping non-cacheable 0.5g bytes w/o tlb mapping cacheable address error w/tlb mapping address error 16t bytes note 2 w/tlb mapping address error 16t bytes note 3 w/tlb mapping ckseg3 cksseg ckseg1 ckseg0 xkseg xkuseg xksseg 32 bits note 1 0.5g bytes w/tlb mapping 0.5g bytes w/o tlb mapping cacheable 2g bytes w/tlb mapping kseg3 ksseg kuseg 0xffff ffff 0.5g bytes w/tlb mapping kseg1 kseg0 0.5g bytes w/o tlb mapping non-cacheable w/o tlb mapping (for details, refer to figure 2-11 .) xkphys 0xe000 0000 0xdfff ffff 0xc000 0000 0xbfff ffff 0xa000 0000 0x9fff ffff 0x8000 0000 0x7fff ffff 0x0000 0000 0xffff ffff ffff ffff 0xffff ffff e 000 0000 0xffff ffff dfff ffff 0xffff ffff c 000 0000 0xffff ffff bfff ffff 0xffff ffff a 000 0000 0xffff ffff 9fff ffff 0xffff ffff 8 000 0000 0xffff ffff 7fff ffff 0xc000 0fff 0000 0000 0xc000 0ffe ffff ffff 0xc000 0000 0000 0000 0xbfff ffff ffff ffff 0x8000 0000 0000 0000 0x7fff ffff ffff ffff 0x4000 1000 0000 0000 0x4000 0 fff ffff ffff 0x4000 0000 0000 0000 0x3fff ffff ffff ffff 0x0000 1000 0000 0000 0x0000 0 fff ffff ffff 0x0000 0000 0000 0000
27 m pd30700,30700l,30710 figure 2-11. details of xkphys area 2.5.2 address translation virtual addresses are translated into physical addresses by the internal tlb (translation lookaside buffer) in page units. the tlb is of full-associative configuration and has 64 entries at the virtual address side and 32 entries at the physical address side. the page size can be changed from 4k bytes to 16m bytes. if a hit of a tlb entry does not occur, a tlb non-coincidence exception occurs in the 32-bit mode and an xtlb non-coincidence exception occurs in the 64-bit mode. if this happens, replace the contents of the tlb by software. figure 2-12 outlines address translation. address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable address error 4 g bytes w/o tlb mapping non-cacheable address error 4g bytes w/o tlb mapping cacheable address error 4g bytes w/o tlb mapping cacheable 0xbfff ffff ffff ffff 0xb800 0001 0000 0000 0xb800 0000 ffff ffff 0xb800 0000 0000 0000 0xb7ff ffff ffff ffff 0xb000 0001 0000 0000 0xb000 0000 ffff ffff 0xb000 0000 0000 0000 0xafff ffff ffff ffff 0xa800 0001 0000 0000 0xa800 0000 ffff ffff 0xa800 0000 0000 0000 0xa7ff ffff ffff ffff 0xa000 0001 0000 0000 0xa000 0000 ffff ffff 0xa000 0000 0000 0000 0x9fff ffff ffff ffff 0x9800 0001 0000 0000 0x9800 0000 ffff ffff 0x9800 0000 0000 0000 0x97ff ffff ffff ffff 0x9000 0001 0000 0000 0x9000 0000 ffff ffff 0x9000 0000 0000 0000 0x8fff ffff ffff ffff 0x8800 0001 0000 0000 0x8800 0000 ffff ffff 0x8800 0000 0000 0000 0x87ff ffff ffff ffff 0x8000 0001 0000 0000 0x8000 0000 ffff ffff 0x8000 0000 0000 0000
28 m pd30700,30700l,30710 figure 2-12. outline of address translation tlb entries are read or written by loading/storing the tlb entry indicated by the index register and the random register from or to the entry hi, entry lo1, entry lo0, and page mask registers. figure 2-13 outlines tlb manipulation. figure 2-13. outline of tlb manipulation y+8 y+1 y x+1 x 0 x? 63 0 asid vpn offset virtual address <1> <2> <3> selector <4> 40 x x? 0 tlb x = 12, 14, 16, 18, 20, 22, 24 y = 31 (in 32-bit mode) 63 (in 64-bit mode) physical address <1> a virtual address page number (vpn) is compared with vpn in tlb. <2> if the two vpns coincide, a page frame number (pfn) indicating the high-order bits of a physical address is output to the selector. <3> if the least significant bit of vpn is 0, an even page is selected; if it is 1, an odd page is selected. the selected page is output to the high-order bits of the physical address. <4> the offset is output to the low-order bits of the physical address without via tlb. entry lo0 register page mask register entry lo1 register entry hi register index register random register
29 m pd30700,30700l,30710 2.6 cache the v r 10000 has a primary instruction cache and primary data cache. in addition, it has a secondary cache interface to connect an external secondary cache. 2.6.1 primary cache (1) primary instruction cache here are the features of the primary instruction cache: ? internal cache memory ? capacity: 32k bytes ? 16-word cache line ? 2-way set associative ? physical index address ? physical tag check (2) primary data cache here are the features of the primary data cache. ? internal cache memory ? capacity: 32k bytes ? 8-word cache line ? 2-bank configuration ? 2-way set associative ? non-blocking method ? write back method ? physical index address ? physical tag check 2.6.2 secondary cache the v r 10000 can use an external secondary cache. the features of the secondary cache are as follows: ? capacity: 512k to 16m bytes ? 16-/32-word cache line ? 2-way set associative ? way prediction table ? write back method ? non-blocking method ? physical index address ? physical tag check
30 m pd30700,30700l,30710 3. fpu internal architecture 3.1 internal function block figure 3-1 shows the internal block of the fpu. the fpu can execute all the floating-point instructions defined by mips isa. figure 3-1. internal block of fpu 3.2 fpu registers (1) floating-point general-purpose registers (fgr) these are physical general-purpose registers that can be directly accessed. thirty-two of these registers are available. the bit length of each register differs depending on the content of the fr bit of the status register. (2) floating-point registers (fpr) these are logical 64-bit registers that hold a floating-point value when a floating-point operation is executed. the number of these registers varies depending on the content of the fr bit of the status register. 64 64 64 64 64 fp register file fp queue v r 10000 internal bus 64 64 fp addition fp multiplication fp division + fp square root data cache internal bus
31 m pd30700,30700l,30710 figure 3-2. registers of fpu (a) when fr bit = 0 (b) when fr bit = 1 (mips i, mips ii) (mips iii, mips iv) 3.3 data format (1) floating-point format the fpu supports ieee754 floating-point operations of 32 bits (single precision) and 64 bits (double precision). (2) fixed-point format a fixed-point value is calculated in the form of 2s complement. floating-point registers (fpr) floating-point general-purpose registers (fgr) floating-point registers (fpr) floating-point general-purpose registers (fgr) fpr0 fpr1 fpr2 fpr3 fpr28 fpr29 fpr30 fpr31 fgr28 fgr29 fgr30 fgr31 fgr0 fgr1 fgr2 fgr3 fgr28 fgr29 fgr30 fgr31 fgr0 fgr1 fgr2 fgr3 (low-order) (high-order) (low-order) (high-order) (low-order) (high-order) (low-order) (high-order) fpr2 fpr0 fpr28 fpr30 31 0 63 0
32 m pd30700,30700l,30710 4. interface 4.1 system interface the i/o timing of the v r 10000 is as follows: ? output starts changing at the rising edge of sysclk. ? input is latched at the rising edge of sysclk. the following two buses are used for system interfacing. ? sysad (63:0) : this bus transfers addresses and data. ? syscmd (11:0) : this bus transfers command data identifiers. both sysad and syscmd are bidirectional buses and are driven by the v r 10000 or external agent. depending on the direction in which they are driven, these buses are in the following two statuses. ? master status : driven by the v r 10000 to issue a processor request. ? slave status : driven by the external agent to issue an external request. the following two cycles are used depending on the information included in the sysad bus. ? address cycle : a valid address is included in the sysad bus. ? data cycle : valid data is included in the sysad bus. next, the interface control signals are briefly explained. ? sysreq : signal used by the v r 10000 to request the right to use the system interface. ? sysgnt : signal used by the external agent to grant the v r 10000 the right to use the system interface. ? sysrel : asserted active when the master of the system interface releases the right of use. ? sysrdrdy : indicates that the external agent is ready to accept a processor read request and upgrade request. ? syswrrdy : indicates that the external agent is ready to accept a processor write request and processor eliminate request. ? sysval : asserted active when the master of the system interface outputs valid data to the sysad and syscmd buses. ? sysstate (2:0) : signal used by the v r 10000 to issue a coherent status request. ? sysresp (4:0) : signal used by the external agent to issue an external end response. ? sysgblperf : signal used by the external agent to indicate that all processor requests have been completed. 4.1.1 setting operating frequency of system interface the v r 10000 can select the operating frequency of the system interface. the clock (pclk) for pipeline operation is generated based on the clock (sysclk) input from an external source. the factor by which sysclk is multiplied to generate pclk is set by using the btmc interface at reset. for details, refer to sysad (9:12) in table 4-1 mode setting in boot time mode .
33 m pd30700,30700l,30710 4.2 secondary cache interface the v r 10000 has a secondary cache control circuit, so that an external secondary cache memory can be connected. the v r 10000 can also selects the operating frequency of the secondary cache interface. scclk, at which the secondary cache is to operate, is generated based on the operating clock (pclk) of the v r 10000. the factor by which sysclk is multiplied to generate pclk is set by using the btmc interface at reset. for details, refer to sysad (9:12) in table 4-1 mode setting in boot time mode . 4.3 clock interface 4.3.1 system interface clock and processor clock the v r 10000 generates a processor clock (pclk), which is the internal operating clock, from the clock (sysclk and sysclk) input to the v r 10000, by using the pll. it always samples the sysclk and sysclk signals during operation, in order to check to see if the following expression is satisfied. pclk = sysclk (sysclkdiv + 1)/2 example where sysclk = 50 mhz and sysclkdiv = 7 pclk = 50 8/2 = 200 mhz 4.3.2 secondary cache clock the v r 10000 supplies clocks for secondary cache (scclk (5:0) and scclk (5:0)) to the external secondary cache. scclk (5:0) are generated from sysclk. the relation between scclk (5:0) and sysclk can be expressed by the following expression. scclk = sysclk (sysclkdiv + 1)/(scclkdiv + 1) example where sysclk = 50 mhz, sysclkdiv = 7, and scclkdiv = 2 scclk = 50 8/3 = 133 mhz 4.4 system configuration example because the v r 10000 employs a cluster bus, it can also support a multi-processor system. examples of configuration of a uni-processor system and a multi-processor system are shown below. 4.4.1 uni-processor system this system uses only one v r 10000, as shown in figure 4-1.
34 m pd30700,30700l,30710 figure 4-1. example of configuration of uni-processor system main memory, i/o external agent sysreq sysgnt sysrel sysrdrdy syswrrdy sysstatepar sysstateval syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysstate(2 : 0) sysresppar sysrespval sysresp (4 : 0) sysreq sysgnt sysrel sysrdrdy syswrrdy sysstatepar sysstateval syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysstate (2 : 0) sysresppar sysrespval sysresp (4 : 0) v r 10000 secondary cache tag secondary cache data sctwr sctcs sctoe wr cs oe wr cs oe data data addr addr sctway sctaglsbaddr scdata (127 : 0) scdatachk (9 : 0) sctag(25 : 0) sctagchk(6 : 0) sc (a, b) addr (18 : 0) sc(a, b)dway sc(a, b)dwr sc(a, b)dcs sc(a, b)doe
35 m pd30700,30700l,30710 4.4.2 multi-processor system up to four v r 10000s can be connected to the cluster bus. while a v r 10000 stands by for a response after it has issued a request, it can receive up to four processings. figure 4-2 shows an example of multi-processor system configuration. figure 4-2. example of configuration of multi-processor system main memory, i/o cluster controller sysrel sysrdrdy syswrrdy sysreq0 sysgnt0 syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysstate0 (2 : 0) sysstatepar0 sysstateval0 sysreq sysgnt sysrel sysrdrdy syswrrdy sysstatepar sysstateval syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysstate (2 : 0) sysresppar sysrespval sysresp (4 : 0) v r 10000 secondary cache tag secondary cache data sctwr sctcs sctoe wr cs oe wr cs oe data data addr addr sctway sctaglsbaddr scdata (127 : 0) scdatachk (9 : 0) sctag (25 : 0) sctagchk (6 : 0) sc (a, b) addr (18 : 0) sc (a, b) dway sc (a, b) dwr sc (a, b) dcs sc (a, b) doe sysreq sysgnt sysrel sysrdrdy syswrrdy sysstatepar sysstateval syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysstate (2 : 0) sysresppar sysrespval sysresp (4 : 0) v r 10000 secondary cache tag secondary cache data sctwr sctcs sctoe wr cs oe wr cs oe data data addr addr sctway sctaglsbaddr scdata (127 : 0) scdatachk (9 : 0) sctag (25 : 0) sctagchk (6 : 0) sc (a, b) addr (18 : 0) sc (a, b) dway sc (a, b) dwr sc (a, b) dcs sc (a, b) doe sysreq1 sysgnt1 sysstate1 (2 : 0) sysstatepar1 sysstateval1 sysresppar sysrespval sysresp (4 : 0) cluster bus
36 m pd30700,30700l,30710 4.5 btmc interface the operation of the v r 10000 is set by the mode bit. the content of the mode bit is stored to the processor via sysad (63:0) at power-on reset or by cold reset sequence while sysgnt is active. the content of the mode bit that is set via sysad (24:0) is stored to bits 24 through 0 of the config register. table 4-1 shows the correspondence between the sysad bus and mode setting in the boot time mode. table 4-1. mode setting in boot time mode (1/2) sysad mode setting v r 10000 v r 12000 0 : 2 kseg0ca: kseg0 cache status 0, 1: rfu 2: non-cacheable 3: cacheable, non-coherent 4: cacheable, coherent exclusive 5: cacheable, coherent exclusive on write 6: rfu 7: non-cacheable, accelerate 3, 4 devnum: processor number 5 cohprcreqtar: issuance destination of processor coherent request 0: external agent 1: all 6 prcelmreq: enables processor eliminate request 0: disabled 1: enabled 7, 8 prcreqmax: number of processor requests that can be kept pending on system bus 0: 1 1: 2 2: 3 3: 4 9 : 12 sysclkdiv: multiple of pclk in respect to sysclk sysclkdiv: multiple of pclk in respect to sysclk 0: rfu 0: rfu 1: 1 1: rfu 2: 1.5 2: rfu 3: 2 3: 2 4: 2.5 4: 2.5 5: 3 5: 3 6: 3.5 6: 3.5 7: 4 7: 4 8 to f: rfu 8: 4.5 9: 5 a: 5.5 b: 6 c: 7 d: 8 e: 9 f: 10 13 scblksize: line size of secondary cache 0: 16 words 1: 32 words
37 m pd30700,30700l,30710 table 4-1. mode setting in boot time mode (2/2) sysad mode setting v r 10000 v r 12000 14 sccoren: ecc error correction of secondary cache data 0: re-access 1: always access 15 memend: endian 0: little endian 1: big endian 16 : 18 scsize: secondary cache size 0: 512k 1: 1m bytes 2: 2m bytes 3: 4m bytes 4: 8m bytes 5: 16m bytes 6 and 7: rfu 19 : 21 scclkdiv: multiple of pclk in respect to scclk scclkdiv: multiple of pclk in respect to scclk 0: rfu 0: rfu 1: 1 1: 1 2: 1.5 2: 1.5 3: 2 3: 2 4: 2.5 4: 2.5 5: 3 5: 3 6 and 7: rfu 6: rfu 7: 4 22 : 24 rfu dsd note 1 : dsd (delay speculative dirty) mode 0 to 3: rfu 4: dsd 5 to 7: rfu 25 : 28 scclktap: internal secondary cache: phase comparison of clock and sysclk (5:0), sysclk (5:0) 0: same phase 1: scclk leads 1/12pclk cycle 2: scclk leads 2/12pclk cycle 3: scclk leads 3/12pclk cycle 4: scclk leads 4/12pclk cycle 5: scclk leads 5/12pclk cycle 6 and 7: undefined 8: scclk leads 6/12pclk cycle 9: scclk leads 7/12pclk cycle a: scclk leads 8/12pclk cycle b: scclk leads 9/12pclk cycle c: scclk leads 10/12pclk cycle d: scclk leads 11/12pclk cycle e and f: undefined 29 rfu 30 odrainsys: processing of system interface signal note 2 31 : 63 rfu notes 1. refer to 4.6 dsd (delay speculative dirty) mode . 2. sysreq, sysrel, syscmd (11:0), syscmdpar, sysad (63: 0), sysadchk (7:0), sysval, sysstate (2:0), sysstatepar, sysstateval, syscorerr, sysuncerr
38 m pd30700,30700l,30710 4.6 dsd (delay speculative dirty) mode (v r 12000 only) the dsd (delay speculative dirty) mode prevents a dirty bit from being set by speculative storing. bit 24 in the boot mode coincides with bit 24 of the config register and sets the dsd mode in the kernel mode and supervisor mode. however, the dsd mode can be also executed in the user mode by setting bit 24 of the status register. bit 24 of the config register is read-only and can be set only during boot time. when the dsd mode has been set, the dirty bit of the secondary cache block of the v r 12000 are not set until the store instruction has become the oldest instruction in the active list and ready to be executed (the dirty bit may be set by an interrupt (and the store instruction is no longer in the speculative status), but the store instruction is not immediately completed). 4.6.1 dsd mode delay the dsd mode delays setting of a dirty bit but slightly slows down the processing speed. this slowdown occurs each time a block is refilled from the main memory if it is necessary to set the dirty bit. it takes 10 cycles to set the dirty bit. during this time, the processor executes the other instructions in parallel. once a block becomes dirty in the secondary cache, this mode does not affect the performance. 4.6.2 secondary cache status in dsd mode the secondary cache in the dsd mode enters the clean exclusive status if a miss hit occurs when the store instruction is no longer the oldest instruction in the pipeline. because the cache is upgraded to the clean exclusive status immediately after a hit occurs in a line in the shared status, bus manipulation is started in the speculative status (the processing speed relatively slows down). 4.6.3 other features the v r 12000 delays loading of the non-coherent cache until this instruction becomes the oldest, regardless of the dsd mode. this is because speculative loading that accesses an address of the xkphys area not mapped as a non- coherent cache may send data to the secondary cache without appropriate coherency check.
39 m pd30700,30700l,30710 5. internal/external control functions 5.1 reset function the following three types of reset functions are available: ? power-on reset ? cold reset ? software reset cold reset and software reset are executed with the power turned on. as a result of reset, the internal status is initialized. however, software reset does not affect the internal clock and secondary cache clock. 5.1.1 power-on reset and cold reset power-on reset and cold reset are executed when the sysgnt and sysrespval signals are deasserted inactive and the sysreset signal is asserted active. during reset, 64-bit data is received from the mode bit, and the internal status of the processor is initialized (for further information, refer to 4.5 btmc interface ). 5.1.2 software reset software reset is executed when the sysgnt and sysrespval signals are deasserted inactive and the sysreset signal is asserted active. as a result, all the statuses of the external interface are initialized, but the internal clock and secondary cache clock continues operating. like the primary and secondary cache, the contents of the cp0 and fpu registers are retained. 5.2 interrupt functions there are two major types of interrupt requests: ? maskable interrupt request ? non-maskable interrupt (nmi) request (1) maskable interrupt requests these interrupts can be masked by using the status register (each interrupt can be serviced independently, or all interrupts can be serviced in batch). there is no priority assigned to the interrupts. (a) hardware interrupt requests (five sources) these interrupts are acknowledged when the corresponding external interrupt request is issued. (b) software interrupt requests (two sources) these interrupts are acknowledged when the ip0 and ip1 bits of the cause register are set. (c) timer interrupt request (1 source) this interrupt is acknowledged when the ip7 bit of the cause register is set because the value of the count register has become equal to the value of the compare register, or when one of the two performance counters has overflown. (2) nmi request (1 source) this is an interrupt request that cannot be masked and is acknowledged when the sysnmi signal is asserted active.
40 m pd30700,30700l,30710 5.3 jtag function the jtag boundary scan function is a mechanism to test mutual connections among the v r 10000 and other components, and not to test the processor itself. as the minimum functions of jtag, the following functions are provided to the v r 10000. functionally, however, the v r 10000 only has the external test function of the jtag boundary scan register. ? tap controller ? jtag instruction register ? jtag bypass register ? jtag boundary scan register
41 m pd30700,30700l,30710 6. instruction set the instructions of the v r 10000 consists of 1 word (32 bits) located at a word boundary, and come in three formats as shown in figure 6-1. because only three types of instructions are provided, decoding instructions is simplified. complicated operations and addressing modes that are not so often used are implemented by a compiler. 6.1 instruction formats the instruction formats of the v r 10000 are shown below. figure 6-1. cpu instruction format 6.2 cpu instruction set list the cpu instructions of the v r 10000 can be classified into an instruction set common to all the v r series processors (isa: instruction set architecture), instruction set that is executed by the v r 4000 series and v r 10000 series (expanded isa), and system control coprocessor instruction set. tables 6-1 through 6-4 list each instruction set. 31 26 25 21 20 16 15 0 op rs rt immediate op target op rs rt rd sa funct 31 26 25 0 31 26 25 21 20 16 15 0 11 10 6 5 i - type (immediate format) j - type (jump format) r - type (register format) op rs rt immediate target rd sa funct 6-bit instruction code 5-bit source register specifier 5-bit target (source/destination) register, or branch condition 16-bit immediate value, branch displacement, or address displacement 26-bit unconditional branch target address 5-bit destination register specifier 5-bit shift amount 6-bit function field
42 m pd30700,30700l,30710 table 6-1. cpu instruction set: mips i (1/2) instruction description format load/store instruction op base rt offset lb load byte lb rt, offset (base) lbu load byte unsigned lbu rt, offset (base) lh load halfword lh rt, offset (base) lhu load halfword unsigned lhu rt, offset (base) lw load word lw rt, offset (base) lwl load word left lwl rt, offset (base) lwr load word right lwr rt, offset (base) sb store byte sb rt, offset (base) sh store halfword sh rt, offset (base) sw store word sw rt, offset (base) swl store word left swl rt, offset (base) swr store word right swr rt, offset (base) alu immediate instruction op rs rt offset addi add immediate addi rt, rs, immediate addiu add immediate unsigned addiu rt, rs, immediate slti set on less than immediate slti rt, rs, immediate sltiu set on less than immediate unsigned sltiu rt, rs, immediate andi and immediate andi rt, rs, immediate ori or immediate ori rt, rs, immediate xori exclusive or immediate xori rt, rs, immediate lui load upper immediate lui rt, immediate 3-operand type instruction op rs rt rd sa funct add add add rd, rs, rt addu add unsigned addu rd, rs, rt sub subtract sub rd, rs, rt subu subtract unsigned subu rd, rs, rt slt set on less than slt rd, rs, rt sltu set on less than unsigned sltu rd, rs, rt and and and rd, rs, rt or or or rd, rs, rt xor exclusive or xor rd, rs, rt nor nor nor rd, rs, rt shift instruction op rs rt rd sa funct sll shift left logical sll rd, rt, sa srl shift right logical srl rd, rt, sa sra shift right arithmetic sra rd, rt, sa sllv shift left logical variable sllv rd, rt, rs srlv shift right logical variable srlv rd, rt, rs srav shift right arithmetic variable srav rd, rt, rs
43 m pd30700,30700l,30710 table 6-1. cpu instruction set: mips i (2/2) instruction description format multiplication/division instruction op rs rt rd sa funct mult multiply mult rs, rt multu multiply unsigned multu rs, rt div divide div rs, rt divu divide unsigned divu rs, rt mfhi move from hi mfhi rd mflo move from lo mflo rd mthi move to hi mthi rs mtlo move to lo mtlo rs jump instruction (1) op target j jump j target jal jump and link jal target jump instruction (2) op rs rt rd sa funct jr jump register jr rs jalr jump and link register jalr rs jalr rs, rd branch instruction (1) op rs rt offset beq branch on equal beq rs, rt, offset bne branch on not equal bne rs, rt, offset blez branch on less than or equal to zero blez rs, offset bgtz branch on greater than zero bgtz rs, offset branch instruction (2) regimm rs sub offset bltz branch on less than zero bltz rs, offset bgez branch on greater than or equal to zero bgez rs, offset bltzal branch on less than zero and link bltzal rs, offset bgezal branch on greater than or equal to zero and link bgezal rs, offset special instruction special rs rt rd sa funct syscall system call syscall break breakpoint break coprocessor instruction (1) op base rt offset lwcz load word to coprocessor z lwcz rt, offset (base) swcz store word from coprocessor z swcz rt, offset (base) coprocessor instruction (2) copz co cofun copz coprocessor z operation copz cofun
44 m pd30700,30700l,30710 table 6-2. cpu instruction set: mips ii instruction description format load/store instruction op base rt offset ll load linked ll rt, offset (base) sc store conditional sc rt, offset (base) branch instruction (1) op rs rt offset beql branch on equal likely beql rs, rt, offset bnel branch on not equal likely bnel rs, rt, offset blezl branch on less than or equal to zero likely blezl rs, offset bgtzl branch on greater than zero likely bgtzl rs, offset branch instruction (2) regimm rs sub offset bltzl branch on less than zero likely bltzl rs, offset bgezl branch on greater than or equal to zero likely bgezl rs, offset bltzall branch on less than zero and link likely bltzall rs, offset bgezall branch on greater than or equal to zero and link likely bgezall rs, offset exception instruction special rs rt rd sa funct tge trap if greater than or equal tge rs, rt tgeu trap if greater than or equal unsigned tgeu rs, rt tlt trap if less than tlt rs, rt tltu trap if less than unsigned tltu rs, rt teq trap if equal teq rs, rt tne trap if not equal tne rs, rt exception immediate instruction regimm rs sub immediate tgei trap if greater than or equal immediate tgei rs, immediate tgeiu trap if greater than or equal immediate unsigned tgeiu rs, immediate tlti trap if less than immediate tlti rs, immediate tltiu trap if less than immediate unsigned tltiu rs, immediate teqi trap if equal immediate teqi rs, immediate tnei trap if not equal immediate tnei rs, immediate special instruction special rs rt rd sa funct sync synchronize sync coprocessor instruction op base rt offset ldcz load doubleword to coprocessor z ldcz rt, offset (base) sdcz store doubleword from coprocessor z sdcz rt, offset (base)
45 m pd30700,30700l,30710 table 6-3. cpu instruction set: mips iii instruction description format load/store instruction op base rt offset ld load doubleword ld rt, offset (base) ldl load doubleword left ldl rt, offset (base) ldr load doubleword right ldr rt, offset (base) lld load linked doubleword lld rt, offset (base) lwu load word unsigned lwu rt, offset (base) scd store conditional doubleword scd rt, offset (base) sd store doubleword sd rt, offset (base) sdl store doubleword left sdl rt, offset (base) sdr store doubleword right sdr rt, offset (base) alu immediate instruction op rs rt immediate daddi doubleword add immediate daddi rt, rs, immediate daddiu doubleword add immediate unsigned daddiu rt, rs, immediate 3-operand type instruction op rs rt rd sa funct dadd doubleword add dadd rd, rs, rt daddu doubleword add unsigned daddu rd, rs, rt dsub doubleword subtract dsub rd, rs, rt dsubu doubleword subtract unsigned dsubu rd, rs, rt shift instruction op rs rt rd sa funct dsll doubleword shift left logical dsll rd, rt, sa dsrl doubleword shfit right logical dsrl rd, rt, sa dsra doubleword shift right arithmetic dsra rd, rt, sa dsllv doubleword shift left logical variable dsllv rd, rt, rs dsrlv doubleword shift right logical variable dsrlv rd, rt, rs dsrav doubleword shift right arithmetic variable dsrav rd, rt, rs dsll32 doubleword shift left logical + 32 dsll32 rd, rt, sa dsrl32 doubleword shift right logical + 32 dsrl32 rd, rt, sa dsra32 doubleword shift right arithmetic +32 dsra32 rd, rt, sa multiplication/division instruction op rs rt rd sa funct dmult doubleword multiply dmult rs, rt dmultu doubleword multiply unsigned dmultu rs, rt ddiv doubleword divide ddiv rs, rt ddivu doubleword divide unsigned ddivu rs, rt
46 m pd30700,30700l,30710 table 6-4. cpu instruction set: mips iv instruction description format 3-operand type instruction op rs rt rd sa funct movn move conditional on not zero movn rd, rs, rt movz move conditional on zero movz rd, rs, rt prefetch instruction op base hint offset pref prefetch pref hint, offset (base) 6.3 fpu instruction set list all the fpu instructions are 32 bits long and located at a word boundary. tables 6-5 through 6-8 list the fpu instruction set. table 6-5. fpu instruction set: mips i instruction description format load/store instruction op base ft offset lwc1 load word to fpu lwc1 ft, offset (base) swc1 store word from fpu swc1 ft, offset (base) transfer instruction cop1 sub rt fs 0 mtc1 move word to fpu mtc1 rt, fs mfc1 move word from fpu mfc1 rt, fs ctc1 move control word to fpu ctc1 rt, fs cfc1 move control word from fpu cfc1 rt, fs conversion instruction cop1 fmt 0 fs fd funct cvt.s.fmt floating-point convert to single floating-point format cvt.s.fmt fd, fs cvt.d.fmt floating-point convert to double floating-point format cvt.d.fmt fd, fs cvt.w.fmt floating-point convert to single fixed-point format cvt.w.fmt fd, fs operation instruction cop1 fmt ft fs fd funct add.fmt floating-point add add.fmt fd, fs, ft sub.fmt floating-point subtract sub.fmt fd, fs, ft mul.fmt floating-point multiply mul.fmt fd, fs, ft div.fmt floating-point divide div.fmt fd, fs, ft abs.fmt floating-point absolute value abs.fmt fd, fs mov.fmt floating-point move mov.fmt fd, fs neg.fmt floating-point negate neg.fmt fd, fs compare instruction cop1 fmt ft fs cc 0 funct c.cond.fmt floating-point compare c.cond.fmt cc, fs, ft fpu branch instruction cop1 bc cc 0 offset bc1t branch on fpu true bc1t cc, offset bc1f branch on fpu false bc1f cc, offset
47 m pd30700,30700l,30710 table 6-6. fpu instruction set: mips ii instruction description format load/store instruction op base ft offset ldc1 load doubleword to fpu ldc1 ft, offset (base) sdc1 store doubleword from fpu sdc1 ft, offset (base) conversion instruction cop1 fmt 0 fs fd funct round.w.fmt floating-point round to single fixed-point format round.w.fmt fd, fs trunc.w.fmt floating-point truncate to single fixed-point format trunc.w.fmt fd, fs ceil.w.fmt floating-point ceiling to single fixed-point format ceil.w.fmt fd, fs floor.w.fmt floating-point floor to single fixed-point format floor.w.fmt fd, fs operation instruction cop1 fmt ft fs fd funct sqrt.fmt floating-point square root sqrt.fmt fd, fs fpu branch instruction cop1 bc cc 0 offset bc1tl branch on fpu true likely bc1tl cc, offset bc1fl branch on fpu false likely bc1fl cc, offset table 6-7. fpu instruction set: mips iii instruction description format transfer instruction cop1 sub rt fs 0 dmtc1 doubleword move to fpu dmtc1 rt, fs dmfc1 doubleword move from fpu dmfc1 rt, fs conversion instruction cop1 fmt 0 fs fd funct cvt.s.fmt floating-point convert to single floating-point format cvt.s.fmt fd, fs cvt.d.fmt floating-point convert to double floating-point format cvt.d.fmt fd, fs cvt.l.fmt floating-point convert to long fixed-point format cvt.l.fmt fd, fs round.l.fmt floating-point round to long fixed-point format round.l.fmt fd, fs trunc.l.fmt floating-point truncate to long fixed-point format trunc.l.fmt fd, fs ceil.l.fmt floating-point ceiling to long fixed-point format ceil.l.fmt fd, fs floor.l.fmt floating-point floor to long fixed-point format floor.l.fmt fd, fs
48 m pd30700,30700l,30710 table 6-8. fpu instruction set: mips iv instruction description format load index instruction op base index 0 fd funct lwxc1 load word indexed to floating-point lwxc1 fd, index (base) ldxc1 load doubleword indexed to floating-point ldxc1 fd, index (base) store index instruction op base index fs 0 funct swxc1 store word indexed from floating-point swxc1 fs, index (base) sdxc1 store doubleword indexed from floating-point sdxc1 fs, index (base) conversion instruction cop1 fmt 0 fs fd funct recip.fmt reciprocal approximation recip.fmt fd, fs rsqrt.fmt reciprocal square root approximation rsqrt.fmt fd, fs multiplication instruction (1) cop1 fmt ft fs fd funct msub.fmt floating-point multiply subtract msub.fmt fd, fr, fs, ft nmsub.fmt floating-point negative multiply subtract nmsub.fmt fd, fr, fs, ft madd.fmt floating-point multiply add madd.fmt fd, fr, fs, ft nmadd.fmt floating-point negative multiply add nmadd.fmt fd, fr, fs, ft movn.fmt floating-point move conditional on not zero movn.fmt fd, fs, ft movz.fmt floating-point move conditional on zero movz.fmt fd, fs, ft operation instruction (2) cop1 fmt cc 0 fs fd funct movf.fmt floating-point move conditional on fpu false movf.fmt fd, fs, cc movt.fmt floating-point move conditional on fpu true movt.fmt fd, fs, cc compare instruction cop1 fmt ft fs cc 0 funct c.cond.fmt floating-point compare c.cond.fmt cc, fs, ft fpu branch instruction cop1 bc cc 0 offset bc1t branch on fpu true bc1t cc, offset bc1f branch on fpu false bc1f cc, offset bc1tl branch on fpu true likely bc1tl cc, offset bc1fl branch on fpu false likely bc1fl cc, offset conditional transfer instruction op rs cc tf rd funct movf move conditional on fpu false movf rd, rs, cc movt move conditional on fpu true movt rd, rs, cc prefetch instruction op base index hint 0 funct prefx prefetch indexed prefx hint, index (base)
49 m pd30700,30700l,30710 6.4 delay of instruction (1) delay of integer instructions table 6-9 shows execution delay of the integer instructions. for details of each instruction, refer to v r 5000, v r 10000 users manual C instruction . table 6-9. integer operation instruction delay time instruction type execution unit pclk repeat rate remark add, set, sub, logical alu1, alu2 1 1 mfhi, mthi, mflo, mtlo 1 1 shift, lui alu1 1 1 conditional branch 1 1 conditional move 1 1 mult alu2 5/6 6 delay of lo/hi multu 6/7 7 delay of lo/hi dmult 9/10 10 delay of lo/hi dmultu 10/11 11 delay of lo/hi div, divu 34/35 35 delay of lo/hi ddiv, ddivu 66/67 67 delay of lo/hi load (except for cp1 instruction) load/store 2 1 in the case of cache hit store 1 in the case of cache hit (2) delay of floating-point instructions table 6-10 shows the execution delay of the floating-point instruction. for details of each instruction, refer to v r 5000, v r 10000 users manual C instruction . table 6-10. floating-point instruction delay time instruction type execution unit pclk repeat rate remark mtc1, dmtc1 alu1 3 1 add, sub, abs, neg, round, fp adder 2 1 trunc, ceil, floor, c.cond cvt.s.w, cvt.s.l 4 2 average value of repeat rate cvt (other than above) 2 1 mul fp multiplier 2 1 mfc1, dmfc1 2 1 conditional move/cvt.s.l 2 1 div.s, recip.s 12 14 div.d, recip.d 19 21 sqrt.s 18 20 sqrt.d 33 35 rsqrt.s 30 20 rsqrt.d 52 35 madd fp adder + fp 2/4 1 2 if other madd instruction uses operation multiplier result lwc1, ldc1, lwxc1, ldxc1 load/store 3 1 in the case of cache hit
50 m pd30700,30700l,30710 7. electrical specifications (1) m pd30700rs-180 and 30700rs-200 absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd C0.5 to +3.8 v input voltage v i C0.5 to v dd + 0.3 v pulse of less than 10 ns C1.5 to v dd + 0.3 v storage temperature t stg C40 to +125 c cautions 1. do not short-circuit two or more outputs at the same time. 2. if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). use the product(s) with these rated values never exceeded. the specifications and conditions shown in dc characteristics and ac characteristics below are the range in which the product(s) operate normally and the quality of the product is guaranteed. operating case temperature (v dd = 3.3 v 0.165 v) parameter symbol condition rating unit operating case temperature t c 0 to 70 c
51 m pd30700,30700l,30710 dc characteristics (t c = 0 to 70 c, v dd = 3.3 v 0.165 v) (a) common to cmos/ttl and hstl parameter symbol condition min. max. unit input capacitance c in 5pf output capacitance c out 7pf power consumption p d 200 mhz (v dd = 3.3 v) 30 w 180 mhz (v dd = 3.3 v) 27 w input leakage power i li 10 m a i/o leakage current i lio 10 m a (b) cmos/ttl parameter symbol condition min. max. unit output supply voltage note 1 v ddq v ddq = v dd 3.135 3.465 v input supply voltage note 2 v ref 1.2 1.6 v high-level output voltage v oh v dd = min., i oh = C4 ma 2.4 v low-level output voltage v ol v dd = max., i ol = 4 ma 0.4 v high-level input voltage v ih 2.0 v dd + 0.3 v low-level input voltage v il C0.5 +0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins. (c) hstl parameter symbol condition min. max. unit output supply voltage note 1 v ddq 1.4 1.6 v input supply voltage note 2 v ref 0.65 0.75 v high-level output threshold voltage note 3 v oh i oh = C4 ma v ddq /2 + 0.3 v low-level output threshold voltage note 3 v ol i ol = 4 ma v ddq /2 C 0.3 v high-level differential input threshold voltage 1 note 4 v ih v ref + 0.1 v dd + 0.3 v low-level differential input threshold voltage 1 note 4 v il C0.3 v dd C 0.1 v high-level differential input threshold voltage 2 note 5 v dih v dil + 0.8 v dd + 0.3 v low-level differential input threshold voltage 2 note 5 v dil C0.3 v dih C 0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins. 3. the v r 10000 supports 1a and 1b of the hstl specifications of sgi. 4. applied to the input pins other than sysclk and sysclk. 5. applied to the sysclk and sysclk pins.
52 m pd30700,30700l,30710 ac characteristics (t c = 0 to 70 c, v dd = 3.3 v 0.165 v) clock parameter parameter symbol condition min. max. unit system clock high-level width t ch t cr , t cf 2.0 ns 0.5 ns system clock low-level width t cl t cr , t cf 2.0 ns 0.5 ns system clock frequency notes 1,2 200-mhz model 50 200 mhz 180-mhz model 45 180 mhz system clock cycle notes 1,2 t cp 200-mhz model 5 20 ns 180-mhz model 5.56 22.2 ns input system clock jitter t ji 125 ps output system clock jitter note 3 t jo 500 ps system clock rise time t cr 2.0 ns system clock fall time t cf 2.0 ns notes 1. the operation of the v r 10000 is guaranteed only when pll operates. 2. the operation is guaranteed when the internal operating frequency is 100 mhz or higher. 3. changes between clock edges are undefined.
53 m pd30700,30700l,30710 system interface parameter (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t do 2.0 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns (b) hstl parameter symbol condition min. max. unit data output delay time t do 1.5 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns secondary cache tag interface parameter applied to sctag (25:0) and sctagchk (6:0) (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t sdo 2.0 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns (b) hstl parameter symbol condition min. max. unit data output delay time t sdo 1.5 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns
54 m pd30700,30700l,30710 (2) m pd30700lrs-225 and 30700lrs-250 (preliminary) absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd C0.5 to +3.3 v input voltage v i C0.5 to v dd + 0.3 v pulse of less than 10 ns C1.5 to v dd + 0.3 v storage temperature t stg C40 to +125 c cautions 1. do not short-circuit two or more outputs at the same time. 2. if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). use the product(s) with these rated values never exceeded. the specifications and conditions shown in dc characteristics and ac characteristics below are the range in which the product(s) operate normally and the quality of the product is guaranteed. operating case temperature (v dd = 2.6 v 0.1 v) parameter symbol condition rating unit operating case temperature t c 0 to 70 c
55 m pd30700,30700l,30710 dc characteristics (t c = 0 to 70 c, v dd = 2.6 v 0.1 v) (a) common to cmos/ttl and hstl parameter symbol condition min. max. unit input capacitance c in 5pf output capacitance c out 7pf power consumption p d 250 mhz (v dd = 2.6 v) 20 w 225 mhz (v dd = 2.6 v) 17 w input leakage power i li 10 m a i/o leakage current i lio 10 m a (b) cmos/ttl parameter symbol condition min. max. unit output supply voltage note 1 v ddq v ddq = v dd 2.5 2.7 v input supply voltage note 2 v ref 1.2 1.6 v high-level output voltage v oh v dd = min., i oh = C4 ma 2.4 v low-level output voltage v ol v dd = max., i ol = 4 ma 0.4 v high-level input voltage v ih 2.0 v dd + 0.3 v low-level input voltage v il C0.5 +0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins. (c) hstl parameter symbol condition min. max. unit output supply voltage note 1 v ddq 1.4 1.6 v input supply voltage note 2 v ref 0.65 0.75 v high-level output threshold voltage note 3 v oh i oh = C4 ma v ddq /2 + 0.3 v low-level output threshold voltage note 3 v ol i ol = 4 ma v ddq /2 C 0.3 v high-level differential input threshold voltage 1 note 4 v ih v ref + 1 v dd + 0.3 v low-level differential input threshold voltage 1 note 4 v il C0.3 v dd C 0.1 v high-level differential input threshold voltage 2 note 5 v dih v dil + 0.8 v dd + 0.3 v low-level differential input threshold voltage 2 note 5 v dil C0.3 v dih C 0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins. 3. the v r 10000 supports 1a and 1b of the hstl specifications of sgi. 4. applied to the input pins other than sysclk and sysclk. 5. applied to the sysclk and sysclk pins.
56 m pd30700,30700l,30710 ac characteristics (t c = 0 to 70 c, v dd = 2.6 v 0.1 v) clock parameter parameter symbol condition min. max. unit system clock high-level width t ch t cr , t cf 2.0 ns 0.5 ns system clock low-level width t cl t cr , t cf 2.0 ns 0.5 ns system clock frequency notes 1, 2 250-mhz model 62.5 250 mhz 225-mhz model 56.3 225 mhz system clock cycle notes 1, 2 t cp 250-mhz model 4 16 ns 225-mhz model 4.44 17.8 ns input system clock jitter t ji 125 ps output system clock jitter note 3 t jo 500 ps system clock rise time t cr 2.0 ns system clock fall time t cf 2.0 ns notes 1. the operation of the v r 10000 is guaranteed only when pll operates. 2. the operation is guaranteed when the internal operating frequency is 100 mhz or higher. 3. changes between clock edges are undefined.
57 m pd30700,30700l,30710 system interface parameter (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t do 2.0 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns (b) hstl parameter symbol condition min. max. unit data output delay time t do 1.5 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns secondary cache tag interface parameter applied to sctag (25:0) and sctagchk (6:0) (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t sdo 2.0 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns (b) hstl parameter symbol condition min. max. unit data output delay time t sdo 1.5 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns
58 m pd30700,30700l,30710 (3) m pd30710rs-300 (preliminary) absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit supply voltage v dd C0.5 to +3.3 v input voltage v i C0.5 to v dd + 0.3 v pulse of less than 10 ns C1.5 to v dd + 0.3 v storage temperature t stg C40 to +125 c cautions 1. do not short-circuit two or more outputs at the same time. 2. if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). use the product(s) with these rated values never exceeded. the specifications and conditions shown in dc characteristics and ac characteristics below are the range in which the product(s) operate normally and the quality of the product is guaranteed. operating case temperature (v dd = 2.6 v 0.1 v) parameter symbol condition rating unit operating case temperature t c 25 to 70 c
59 m pd30700,30700l,30710 dc characteristics (t c = 25 to 70 c, v dd = 2.6 v 0.1 v) (a) common to cmos/ttl and hstl parameter symbol condition min. max. unit input capacitance c in 5pf output capacitance c out 7pf power consumption p d 300 mhz (v dd = 2.6 v) 30 w input leakage power i li 10 m a i/o leakage current i lio 10 m a (b) cmos/ttl parameter symbol condition min. max. unit output supply voltage note 1 v ddq v ddq = v dd 2.5 2.7 v input supply voltage note 2 v ref 1.2 1.6 v high-level output voltage v oh v dd = min., i oh = C4 ma 2.4 v low-level output voltage v ol v dd = max., i ol = 4 ma 0.4 v high-level input voltage v ih 2.0 v dd + 0.3 v low-level input voltage v il C0.5 +0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins. (c) hstl parameter symbol condition min. max. unit output supply voltage note 1 v ddq 1.4 1.6 v input supply voltage note 2 v ref 0.65 0.75 v high-level output threshold voltage note 3 v oh i oh = C4 ma v ddq /2 + 0.3 v low-level output threshold voltage note 3 v ol i ol = 4 ma v ddq /2 C 0.3 v high-level differential input threshold voltage 1 note 4 v ih v ref + 0.1 v dd + 0.3 v low-level differential input threshold voltage 1 note 4 v il C0.3 v dd C 0.1 v high-level differential input threshold voltage 2 note 5 v dih v dil + 0.8 v dd + 0.3 v low-level differential input threshold voltage 2 note 5 v dil C0.3 v dih C 0.8 v notes 1. v ddq is applied to the v dd qsc and v dd qsys pins. 2. v ref is applied to the v ref sc and v ref sys pins 3. the v r 12000 supports 1a and 1b of the hstl specifications of sgi. 4. applied to the input pins other than sysclk and sysclk. 5. applied to the sysclk and sysclk pins.
60 m pd30700,30700l,30710 ac characteristics (t c = 25 to 70 c, v dd = 2.6 v 0.1 v) clock parameter parameter symbol condition min. max. unit system clock high-level width t ch t cr , t cf 2.0 ns 0.5 ns system clock low-level width t cl t cr , t cf 2.0 ns 0.5 ns system clock frequency notes 1, 2 300-mhz model 30 300 mhz system clock cycle notes 1, 2 t cp 300-mhz model 3.33 33.3 ns input system clock jitter t ji 125 ps output system clock jitter note 3 t jo 500 ps system clock rise time t cr 2.0 ns system clock fall time t cf 2.0 ns notes 1. the operation of the v r 12000 is guaranteed only when pll operates. 2. the operation is guaranteed when the internal operating frequency is 100 mhz or higher. 3. changes between clock edges are undefined.
61 m pd30700,30700l,30710 system interface parameter (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t do 2.0 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns (b) hstl parameter symbol condition min. max. unit data output delay time t do 1.5 ns data input setup time t ds 1.0 ns data input hold time t dh 1.0 ns secondary cache tag interface parameter applied to sctag (25:0) and sctagchk (6:0) (a) cmos/ttl parameter symbol condition min. max. unit data output delay time t sdo 2.0 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns (b) hstl parameter symbol condition min. max. unit data output delay time t sdo 1.5 ns data input setup time t sds 1.5 ns data input hold time t sdh 0.5 ns
62 m pd30700,30700l,30710 timing chart secondary cache interface timing secondary cache clock jitter sccik output input t do t sdo t sds t do t do t ds t dh t sdh sctaglsbaddr scadoe scbdoe scadwr scbdwr scadcs scbdcs sctway sctoe sctwr sctcs scdata (127 : 0) scdatachk (9 : 0) scaaddr (18 : 0) scbaddr (18 : 0) sctag (25 : 0) sctagchk (6 : 0) output input t jo t jo (v ol + v oh )/2 sccik
63 m pd30700,30700l,30710 system interface timing system clock system clock jitter syscik t do t dh t ds t do t do t ds t dh sysrel syscmdpar sysval syscmd (11 : 0) sysad (63 : 0) sysadchk (7 : 0) sysreq sysstatepar sysstateval syscorerr sysuncerr sysstate (2 : 0) sysresp (4 : 0) sysgnt sysrdrdy syswrrdy sysresppar sysrespval sysreset sysnmi sysgblperf syscyc output input input t cp sysclk t ch v dih v dil t cl t cr t cf t ji t ji (v dil + v dih )/2 syscik
64 m pd30700,30700l,30710 8. push-pull output buffer circuit the configuration of the push-pull output buffer circuit is shown below. push-pull output buffer circuit (without load of termination) push-pull output buffer circuit (with load of termination) v ccq v ref v ref v ccq v ref v ccq v ccq v ref
65 m pd30700,30700l,30710 9. package drawing w 1 u x index mark y w 2 v a b b a f g c d q l n m c c a s b s *2 *1 l c i j h x599rs-50a item millimeters inches a b c d e f g h i j 47.50?.25 47.50?.25 1.27 (t.p.) 1.27 (t.p.) 0.70 max. 29.00 l 0.76?.13 3.81?.38 2.54?.25 0.20 29.00 2.16 n 1.870?.010 1.142 1.142 0.085 0.050 (t.p.) 0.050 (t.p.) 0.028 max. 0.100?.010 0.150?.015 0.030 0.008 1.870?.010 0.30 q 0.012 2.16 r 43.18 s 0.085 1.700 43.18 t 32.54 u 1.700 1.281 32.54 v 37.00 w 1 1.281 1.457 37.00 w 2 30.00 x 1.457 1.181 30.00 y 1.181 note *1 each land centerline is located within 0.30 mm (0.012 inch) of its true position (t.p.) at least material condition. *2 each land centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 599 pin ceramic lga +0.005 ?.006 s e t r
66 m pd30700,30700l,30710 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
67 m pd30700,30700l,30710 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
m pd30700,30700l,30710 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. this product employs technology which is restricted by the export control regulations of the united states of america. permission of the united states government might be required in case of exporting this product or products in which this product is installed. related documents: v r 10000, v r 12000 users manual (u10278e) v r 5000, v r 10000 users manual - instruction (u12754e) the related documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4000, v r 4200, v r 4400, v r 5000, v r 10000, v r 12000, and v r series are trademarks of nec corporation. mips and andes are trademarks of mips technologies, inc. unix is a registered trademark licensed by x/open company limited in the us and other countries. windows nt is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries.

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